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In semiconductor manufacturing, the 3nm process is the next die shrink after the 5 nm MOSFET (metal–oxide–semiconductor field-effect transistor) technology node. South Korean chipmaker Samsung started shipping its 3 nm gate all around (GAA) process, named 3GAA, in mid-2022.[1][2] On 29 December 2022, Taiwanese chip manufacturer TSMC announced that volume production using its 3 nm semiconductor node (N3) was underway with good yields.[3] An enhanced 3 nm chip process called "N3E" may have started production in 2023.[4] American manufacturer Intel planned to start 3 nm production in 2023.[5][6][7]

Samsung's 3 nm process is based on GAAFET (gate-all-around field-effect transistor) technology, a type of multi-gate MOSFET technology, while TSMC's 3nm process still uses FinFET (fin field-effect transistor) technology,[8] despite TSMC developing GAAFET transistors.[9] Specifically, Samsung plans to use its own variant of GAAFET called MBCFET (multi-bridge channel field-effect transistor).[10] Intel's process (dubbed "Intel 3", without the "nm" suffix) will use a refined, enhanced and optimized version of FinFET technology compared to its previous process nodes in terms of performance gained per watt, use of EUV lithography, and power and area improvement.[11]

Projected node properties according to International Roadmap for Devices and Systems (2021)[12]
Node
name		 Gate
pitch		 Metal
pitch		 Year
5 nm 51 nm 30 nm 2020
3 nm 48 nm 24 nm 2022
2 nm 45 nm 20 nm 2025
1 nm 40 nm 16 nm 2027

The term "3 nanometer" has no direct relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3nm node is expected to have a contacted gate pitch of 48 nanometers, and a tightest metal pitch of 24 nanometers.[12]

However, in real world commercial practice, 3nm is used primarily as a marketing term by individual microchip manufacturers (foundries) to refer to a new, improved generation of silicon semiconductor chips in terms of increased transistor density (i.e. a higher degree of miniaturization), increased speed and reduced power consumption.[13][14] There is no industry-wide agreement among different manufacturers about what numbers would define a 3nm node.[15] Typically the chip manufacturer refers to its own previous process node (in this case the 5nm node) for comparison. For example, TSMC has stated that its 3nm FinFET chips will reduce power consumption by 25–30% at the same speed, increase speed by 10–15% at the same amount of power and increase transistor density by about 33% compared to its previous 5 nm FinFET chips.[16][17] On the other hand, Samsung has stated that its 3nm process will reduce power consumption by 45%, improve performance by 23%, and decrease surface area by 16% compared to its previous 5 nm process.[18] EUV lithography faces new challenges at 3 nm which lead to the required use of multipatterning.[19]

History

Research and technology demos

In 2003, a research team at NEC fabricated the first MOSFETs with a channel length of 3 nm, using the PMOS and NMOS processes.[20][21] In 2006, a team from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center, developed a 3 nm width multi-gate MOSFET, the world's smallest nanoelectronic device, based on gate-all-around (GAAFET) technology.[22][23]

Commercialization history

In late 2016, TSMC announced plans to construct a 5 nm–3 nm node semiconductor fabrication plant with a co-commitment investment of around US$15.7 billion.[24]

In 2017, TSMC announced it was to begin construction of the 3nm semiconductor fabrication plant at the Tainan Science Park in Taiwan.[25] TSMC plans to start volume production of the 3nm process node in 2023.[26][27][28][29][30]

In early 2018, IMEC (Interuniversity Microelectronics Centre) and Cadence stated they had taped out 3nm test chips, using extreme ultraviolet lithography (EUV) and 193 nm immersion lithography.[31]

In early 2019, Samsung presented plans to manufacture 3nm GAAFET (gate-all-around field-effect transistors) at the 3nm node in 2021, using its own MBCFET transistor structure that uses nanosheets; delivering a 35% performance increase, 50% power reduction and a 45% reduction in area when compared with 7 nm.[32][33][34] Samsung's semiconductor roadmap also included products at 8, 7, 6, 5, and 4 nm nodes.[35][36]

In December 2019, Intel announced plans for 3nm production in 2025.[37]

In January 2020, Samsung announced the production of the world's first 3nm GAAFET process prototype, and said that it is targeting mass production in 2021.[38]

In August 2020, TSMC announced details of its "N3" process, which is new rather than being an improvement over its N5 process.[39] Compared with the N5 process, the N3 process should offer a 10–15% (1.10–1.15×) increase in performance, or a 25–35% (1.25–1.35×) decrease in power consumption, with a 1.7× increase in logic density (a scaling factor of 0.58), a 20% increase (0.8 scaling factor) in SRAM cell density, and a 10% increase in analog circuitry density. Since many designs include considerably more SRAM than logic, (a common ratio being 70% SRAM to 30% logic) die shrinks are expected to only be of around 26%. TSMC was planning volume production in the second half of 2022.[40][needs update]

In July 2021, Intel presented brand new process technology roadmap, according to which Intel 3 process (previously named Intel 7+), the company's second node to use EUV and the last one to use FinFET before switching to Intel's RibbonFET transistor architecture, is now scheduled to enter product manufacturing phase in H2 2023.[5][needs update]

In October 2021, Samsung adjusted earlier plans and announced that the company is scheduled to start producing its customers' first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023.[41][needs update]

In June 2022, at TSMC Technology Symposium, the company shared details of its N3E process technology scheduled for volume production in 2023 H2: 1.6× higher logic transistor density, 1.3× higher chip transistor density, 10–15% higher performance at iso power or 30–35% lower power at ISO performance compared to TSMC N5 v1.0 process technology, FinFLEX technology, allowing to intermix libraries with different track heights within a block etc. TSMC also introduced new members of 3nm process family: high-density variant N3S, high-performance variants N3P and N3X, and N3RF for RF applications.[42][43][44]

In June 2022, Samsung started "initial" production of a low-power, high-performance chip using 3nm process technology with GAA architecture.[1][45] According to industry sources, Qualcomm has reserved some of 3nm production capacity from Samsung.[46]

On 25 July 2022, Samsung celebrated the first shipment of 3nm Gate-All-Around chips to a Chinese cryptocurrency mining firm PanSemi.[47][48][49][50] It was revealed that the newly introduced 3 nm MBCFET process technology offers 16% higher transistor density,[51] 23% higher performance or 45% lower power draw compared to an unspecified 5 nm process technology.[52] Goals for the second-generation 3nm process technology include up to 35% higher transistor density,[51] further reduction of power draw by up to 50% or higher performance by 30%.[52][53][51]

On 29 December 2022, TSMC announced that volume production using its 3nm process technology N3 is underway with good yields.[3] The company plans to start volume manufacturing using refined 3nm process technology called N3E in the second half of 2023.[54]

In December 2022, at IEDM 2022 conference, TSMC disclosed a few details about their 3nm process technologies: contacted gate pitch of N3 is 45 nm, minimum metal pitch of N3E is 23 nm, and SRAM cell area is 0.0199 μm2 for N3 and 0.021 μm2 for N3E (same as in N5). For N3E process, depending on the number of fins in cells used for design, area scaling compared to N5 2–2 fin cells ranges from 0.64x to 0.85x, performance gains range from 11% to 32% and energy savings range from 12% to 30% (the numbers refer to Cortex-A72 core). TSMC's FinFlex technology allows to intermix cells with different number of fins in a single chip.[55][56][57][58]

Reporting from IEDM 2022, semiconductor industry expert Dick James stated that TSMC's 3nm processes offered only incremental improvements, because limits have been reached for fin height, gate length, and number of fins per transistor (single fin). After implementation of features such as single diffusion break, contact over active gate and FinFlex, there will be no more room left for improvement of FinFET-based process technologies.[59]

In April 2023, at its Technology Symposium, TSMC revealed some details about their N3P and N3X processes the company had introduced earlier: N3P will offer 5% higher speed or 5–10% lower power and 1.04× higher "chip density" compared to N3E, while N3X will offer 5% speed gain at the cost of ~3.5× higher leakage and the same density compared to N3P. N3P is scheduled to enter volume production in the second half of 2024, and N3X will follow in 2025.[60]

In July 2023, semiconductor industry research firm TechInsights said it has found that Samsung's 3 nm GAA (gate-all-around) process has been incorporated into the crypto miner ASIC (Whatsminer M56S++) from a Chinese manufacturer, MicroBT.[61]

On 7 September 2023, MediaTek and TSMC announced that MediaTek have developed their first 3nm chip, volume production is expected to commence in 2024.[62]

3 nm process nodes

Samsung[41][63][64][65] TSMC[66] Intel[5]
Process name 3GAE
SF3E 		3GAP
SF3 		N3
(a.k.a. N3B)[67] 		N3E N3P N3X 3
Transistor type MBCFET FinFET
Transistor density 150 μm−2[64] 190 μm−2[68] 197 μm−2[44] 216 μm−2[69] 224 μm−2[70] Un­known
SRAM bit-cell size Un­known Un­known 0.0199 μm2[57] 0.021 μm2[57] Un­known Un­known Un­known
Transistor gate pitch 40 nm Un­known 45 nm[57] 48 nm[69] Un­known Un­known 50 nm
Interconnect pitch 32 nm Un­known Un­known 23 nm[57] Un­known Un­known 30 nm
Release status 2022 risk production[41]
2022 production[1]
2022 shipping[2] 		2024 Q1 risk production[71]
2024 H2 production[68] 		2021 risk production
2022 H2 volume production[66][3]
2023 H1 shipping for revenue[72] 		2023 H2 production[66] 2024 H2 production[60] 2025 production[60] 2024 H1 product manufacturing[73]
2024 H2 shipping for revenue[74]

References

  1. ^ a b c "Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture" (Press release). Samsung. Archived from the original on 30 June 2022. Retrieved 30 June 2022.
  2. ^ a b "History is made! Samsung beats out TSMC and starts shipping 3nm GAA chipsets". 25 July 2022. Archived from the original on 23 August 2022. Retrieved 23 August 2022.
  3. ^ a b c "TSMC Kicks Off 3nm Production: A Long Node to Power Leading Chips". Tom's Hardware. 29 December 2022.
  4. ^ Ramish Zafar (4 March 2022). "TSMC Exceeds 3nm Yield Expectations & Production Can Start Sooner Than Planned". wccftech.com. Archived from the original on 16 March 2022. Retrieved 19 March 2022.
  5. ^ a b c Cutress, Dr Ian. "Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?!". AnandTech. Archived from the original on 3 November 2021. Retrieved 27 July 2021.
  6. ^ Gartenberg, Chaim (26 July 2021). "Intel has a new architecture roadmap and a plan to retake its chipmaking crown in 2025". The Verge. Archived from the original on 20 December 2021. Retrieved 22 December 2021.
  7. ^ "Intel Technology Roadmaps and Milestones". Intel. Archived from the original on 16 July 2022. Retrieved 17 February 2022.
  8. ^ Cutress, Dr Ian. "Where are my GAA-FETs? TSMC to Stay with FinFET for 3nm". AnandTech. Archived from the original on 2 September 2020. Retrieved 12 September 2020.
  9. ^ "TSMC Plots an Aggressive Course for 3nm Lithography and Beyond – ExtremeTech". Extremetech.com. Archived from the original on 22 September 2020. Retrieved 12 September 2020.
  10. ^ "Samsung at foundry event talks about 3nm, MBCFET developments". Techxplore.com. Archived from the original on 22 November 2021. Retrieved 22 November 2021.
  11. ^ Patrick Moorhead (26 July 2021). "Intel Updates IDM 2.0 Strategy With New Node Naming And Transistor And Packaging Technologies". Forbes. Archived from the original on 18 October 2021. Retrieved 18 October 2021.
  12. ^ a b INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: More Moore, IEEE, 2021, p. 7, archived from the original on 7 August 2022, retrieved 7 August 2022
  13. ^ "TSMC's 7nm, 5nm, and 3nm "are just numbers... it doesn't matter what the number is"". Pcgamesn.co. 10 September 2019. Archived from the original on 17 June 2020. Retrieved 20 April 2020.
  14. ^ Samuel K. Moore (21 July 2020). "A Better Way to Measure Progress in Semiconductors: It's time to throw out the old Moore's Law metric". IEEE Spectrum. IEEE. Archived from the original on 2 December 2020. Retrieved 20 April 2021.
  15. ^ INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: More Moore, IEEE, 2021, p. 6, archived from the original on 7 August 2022, retrieved 7 August 2022, according to which "There is not yet a consensus on the node naming across different foundries and integrated device manufacturers (IDMs)".
  16. ^ Jason Cross (25 August 2020). "TSMC details its future 5nm and 3nm manufacturing processes—here's what it means for Apple silicon". Macworld. Archived from the original on 20 April 2021. Retrieved 20 April 2021.
  17. ^ Anton Shilov (31 August 2020). "The future of leading-edge chips according to TSMC: 5nm, 4nm, 3nm and beyond". Techradar.com. Archived from the original on 20 April 2021. Retrieved 20 April 2021.
  18. ^ "Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture". 30 June 2022. Archived from the original on 8 July 2022. Retrieved 8 July 2022.
  19. ^ Chen, Frederick (17 July 2022). "EUV's Pupil Fill and Resist Limitations at 3nm". LinkedIn. Archived from the original on 29 July 2022.
  20. ^ Schwierz, Frank; Wong, Hei; Liou, Juin J. (2010). Nanometer CMOS. Pan Stanford Publishing. p. 17. ISBN 9789814241083. Archived from the original on 24 May 2020. Retrieved 11 October 2019.
  21. ^ Wakabayashi, Hitoshi; Yamagami, Shigeharu; Ikezawa, Nobuyuki; Ogura, Atsushi; Narihiro, Mitsuru; Arai, K.; Ochiai, Y.; Takeuchi, K.; Yamamoto, T.; Mogami, T. (December 2003). Sub-10-nm planar-bulk-CMOS devices using lateral junction control. IEEE International Electron Devices Meeting 2003. pp. 20.7.1–20.7.3. doi:10.1109/IEDM.2003.1269446. ISBN 0-7803-7872-5. S2CID 2100267.
  22. ^ "Still Room at the Bottom (nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )", Nanoparticle News, 1 April 2006, archived from the original on 6 November 2012
  23. ^ Lee, Hyunjin; Choi, Yang-Kyu; Yu, Lee-Eun; Ryu, Seong-Wan; Han, Jin-Woo; Jeon, K.; Jang, D.Y.; Kim, Kuk-Hwan; Lee, Ju-Hyun; et al. (June 2006). "Sub-5nm All-Around Gate FinFET for Ultimate Scaling". 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers. pp. 58–59. doi:10.1109/VLSIT.2006.1705215. hdl:10203/698. ISBN 978-1-4244-0005-8. S2CID 26482358.
  24. ^ Patterson, Alan (12 December 2016), "TSMC Plans New Fab for 3nm", EE Times, retrieved 22 July 2023
  25. ^ Patterson, Alan (2 October 2017), "TSMC Aims to Build World's First 3-nm Fab", EE Times, retrieved 22 July 2023
  26. ^ Zafar, Ramish (15 May 2019). "TSMC To Commence 2nm Research In Hsinchu, Taiwan Claims Report". Wccftech.com. Archived from the original on 7 November 2020. Retrieved 6 December 2019.
  27. ^ "TSMC to start production on 5nm in second half of 2020, 3nm in 2022". Techspot.com. 8 December 2019. Archived from the original on 19 December 2019. Retrieved 12 January 2020.
  28. ^ Armasu 2019-12-06T20:26:59Z, Lucian (6 December 2019). "Report: TSMC To Start 3nm Volume Production In 2022". Tom's Hardware. Archived from the original on 15 September 2022. Retrieved 19 December 2019.{{cite web}}: CS1 maint: numeric names: authors list (link)
  29. ^ "TSMC 3nm process fab starts construction - mass production in 2023". Gizchina.com. 25 October 2019. Archived from the original on 12 January 2020. Retrieved 12 January 2020.
  30. ^ Friedman, Alan (27 October 2019). "TSMC starts constructing facilities to turn out 3nm chips by 2023". Phone Arena. Archived from the original on 12 January 2020. Retrieved 12 January 2020.
  31. ^ "Imec and Cadence Tape Out Industry's First 3nm Test Chip". Cadence (Press release). 28 February 2018. Retrieved 18 April 2019.
  32. ^ "Samsung Unveils 3nm Gate-All-Around Design Tools - ExtremeTech". ExtremeTech. Retrieved 22 July 2023.
  33. ^ Armasu, Lucian (11 January 2019), "Samsung Plans Mass Production of 3nm GAAFET Chips in 2021", Tom's Hardware, archived from the original on 6 December 2019, retrieved 6 December 2019
  34. ^ Samsung: 3nm process is one year ahead of TSMC in GAA and three years ahead of Intel, 6 August 2019, archived from the original on 15 September 2022, retrieved 18 April 2019
  35. ^ Armasu, Lucian (25 May 2017), "Samsung Reveals 4nm Process Generation, Full Foundry Roadmap", Tom's Hardware, archived from the original on 15 September 2022, retrieved 18 April 2019
  36. ^ Cutress, Ian. "Samsung Announces 3nm GAA MBCFET PDK, Version 0.1". AnandTech. Archived from the original on 14 October 2019. Retrieved 19 December 2019.
  37. ^ Cutress, Dr Ian. "Intel's Manufacturing Roadmap from 2019 to 2029: Back Porting, 7nm, 5nm, 3nm, 2nm, and 1.4 nm". AnandTech. Archived from the original on 12 January 2021. Retrieved 11 December 2019.
  38. ^ Broekhuijsen 2020-01-03T16:28:57Z, Niels (3 January 2020). "Samsung Prototypes First Ever 3nm GAAFET Semiconductor". Tom's Hardware. Archived from the original on 15 September 2022. Retrieved 10 February 2020.{{cite web}}: CS1 maint: numeric names: authors list (link)
  39. ^ Shilov, Anton. "TSMC: 3nm EUV Development Progress Going Well, Early Customers Engaged". AnandTech. Archived from the original on 3 September 2020. Retrieved 12 September 2020.
  40. ^ "TSMC roadmap update: N3E in 2024, N2 in 2026, major changes incoming". AnandTech. 22 April 2022. Archived from the original on 9 May 2022. Retrieved 12 May 2022.
  41. ^ a b c "Samsung Foundry Innovations Power the Future of Big Data, AI/ML and Smart, Connected Devices" (Press release). Samsung. 7 October 2021. Archived from the original on 8 April 2022. Retrieved 23 March 2022.
  42. ^ "TSMC Technology Symposium Review". SemiWiki. 22 June 2022.
  43. ^ "TSMC Readies Five 3nm Process Technologies, Adds FinFlex For Design Flexibility". AnandTech. 16 June 2022.
  44. ^ a b "N3E Replaces N3; Comes In Many Flavors". WikiChip Fuse. 4 September 2022.
  45. ^ "Samsung Starts 3nm Production: The Gate-All-Around (GAAFET) Era Begins". AnandTech. 30 June 2022. Archived from the original on 7 July 2022. Retrieved 7 July 2022.
  46. ^ "Samsung Electronics begins 'trial production' of 3-nano foundry...The first customer is a Chinese ASIC company". TheElec. 28 June 2022. Archived from the original on 28 July 2022. Retrieved 28 July 2022.
  47. ^ "Samsung's 3nm trial production run this week to make Bitcoin miner chips". SamMobile. 28 June 2022. Archived from the original on 27 July 2022. Retrieved 27 July 2022.
  48. ^ "Samsung ships its first set of 3nm chips, marking an important milestone". SamMobile. 25 July 2022. Archived from the original on 27 July 2022. Retrieved 27 July 2022.
  49. ^ "Samsung celebrates the first shipment of 3nm Gate-All-Around chips". www.gsmarena.com. 25 July 2022. Archived from the original on 26 July 2022. Retrieved 26 July 2022.
  50. ^ "Samsung Electronics Holds 3 Nano Foundry Mass Production Shipment Ceremony" (Press release). Samsung. 25 July 2022.
  51. ^ a b c "Samsung holds ceremony to mark 1st shipment of most advanced 3nm chips". Yonhap News Agency. 25 July 2022. Archived from the original on 28 July 2022. Retrieved 28 July 2022.
  52. ^ a b "Samsung Begins Chip Production Using 3nm Process Technology with GAA Architecture". BusinessWire. 29 June 2022. Archived from the original on 28 July 2022. Retrieved 28 July 2022.
  53. ^ "Samsung starts shipping world's first 3nm chips". The Korea Herald. 25 July 2022. Archived from the original on 27 July 2022. Retrieved 27 July 2022.
  54. ^ "TSMC's 3nm Journey: Slow Ramp, Huge Investments, Big Future". AnandTech. 17 January 2023.
  55. ^ Patel, Dylan (21 December 2022). "TSMC's 3nm Conundrum, Does It Even Make Sense? – N3 & N3E Process Technology & Cost Detailed". SemiAnalysis.
  56. ^ Patel, Dylan (2 February 2023). "IEDM 2022 Round-Up". SemiAnalysis.
  57. ^ a b c d e Jones, Scotten (1 February 2023). "IEDM 2022 – TSMC 3nm". SemiWiki.
  58. ^ Schor, David (14 December 2022). "IEDM 2022: Did We Just Witness The Death Of SRAM?". WikiChip Fuse.
  59. ^ James, Dick. "TSMC Reveals 3nm Process Details". TechInsights. Retrieved 16 February 2023.
  60. ^ a b c "TSMC Details 3nm Evolution: N3E On Schedule, N3P and N3X To Deliver 5% Performance Gains". AnandTech. 26 April 2023.
  61. ^ "TechInsights: Samsung's 3nm GAA process identified in a crypto-mining ASIC designed by China startup MicroBT". DIGITIMES. 18 July 2023. Retrieved 21 July 2023.
  62. ^ Neowin ·, Omer Dursun (7 September 2023). "MediaTek develops its first 3nm chip using TSMC process, coming in 2024". Neowin. Retrieved 7 September 2023.
  63. ^ "Can TSMC maintain their process technology lead". SemiWiki. 29 April 2020. Archived from the original on 13 May 2022. Retrieved 14 May 2022.
  64. ^ a b "Samsung 3nm GAAFET Enters Risk Production; Discusses Next-Gen Improvements". WikiChip Fuse. 5 July 2022.
  65. ^ "Samsung Foundry Vows to Surpass TSMC within Five Years". AnandTech.
  66. ^ a b c "TSMC 3nm". www.tsmc.com. 15 April 2022. Archived from the original on 20 April 2022. Retrieved 15 April 2022.
  67. ^ Shilov, Anton. "TSMC: Performance-Optimized 3nm N3P Process on Track for Mass Production This Year". AnandTech. Retrieved 25 September 2024.
  68. ^ a b "Samsung Exynos W1000 Processor: A Dive into the 3nm Gate-All-Around Process". 18 July 2024.
  69. ^ a b "TSMC N3, and Challenges Ahead". 27 May 2023.
  70. ^ "TSMC Details 3nm Evolution: N3E On Schedule, N3P and N3X To Deliver 5% Performance Gains". 26 April 2023.
  71. ^ "Samsung's 2nd-Gen 3nm process, SF3, has begun trial production". 21 January 2024.
  72. ^ "TSMC Q2 2022 Earnings Call" (PDF). TSMC. 14 July 2022. Archived (PDF) from the original on 15 July 2022. Retrieved 22 July 2022.
  73. ^ "IFS Reborn as Intel Foundry: Expanded Foundry Business Adds 14A Process to Roadmap".
  74. ^ Cutress, Dr Ian (17 February 2022). "Intel Discloses Multi-Generation Xeon Scalable Roadmap: New E-Core Only Xeons in 2024". AnandTech. Archived from the original on 15 March 2022. Retrieved 23 March 2022.

Further reading

  • Lapedus, Mark (21 June 2018), "Big Trouble At 3nm", semiengineering.com
  • Bae, Geumjong; Bae, D.-I.; Kang, M.; Hwang, S.M.; Kim, S.S.; Seo, B.; Kwon, T.Y.; Lee, T.J.; Moon, C.; Choi, Y.M.; Oikawa, K.; Masuoka, S.; Chun, K.Y.; Park, S.H.; Shin, H.J.; Kim, J.C.; Bhuwalka, K.K.; Kim, D.H.; Kim, W.J.; Yoo, J.; Jeon, H.Y.; Yang, M.S.; Chung, S.-J.; Kim, D.; Ham, B.H.; Park, K.J.; Kim, W.D.; Park, S.H.; Song, G.; et al. (December 2018). 3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications. 2018 IEEE International Electron Devices Meeting (IEDM). pp. 28.7.1–28.7.4. doi:10.1109/IEDM.2018.8614629. ISBN 978-1-7281-1987-8. S2CID 58673284.
Preceded by
5 nm (FinFET) 		MOSFET semiconductor device fabrication process Succeeded by
2 nm (GAAFET)
source: http://en.m.wikipedia.org/wiki/3_nm_process